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AMD's Zen 6: Revolutionizing Interconnects with Sea-of-Wires

9/29/2025

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Summary

Story summary

AMD plans to replace Serializer/Deserializer (SERDES)-based interconnect with a 'sea-of-wires' approach in Zen 6 to cut latency and power.
Strix Halo APUs show the transition, with pad fields replacing SERDES blocks.
The design uses TSMC's InFO-oS packaging and redistribution layers.
Challenges include signal integrity, thermal behavior, and yield; if successful, Zen 6 could gain significant efficiency and faster memory access.

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Story summary

AMD plans to replace Serializer/Deserializer (SERDES)-based interconnect with a 'sea-of-wires' approach in Zen 6 to cut latency and power.
Strix Halo APUs show the transition, with pad fields replacing SERDES blocks.
The design uses TSMC's InFO-oS packaging and redistribution layers.
Challenges include signal integrity, thermal behavior, and yield; if successful, Zen 6 could gain significant efficiency and faster memory access.