Full Breakdown
Samsung and Taiwan Semiconductor Manufacturing Co. (TSMC) Commit to Advanced Semiconductor Materials Lithography (ASML)’s High-NA EUV Lithography and 12-Inch Photomask Initiative
9/9/2026, 8:28:20 AM
Core Event
On September 8, 2026 Samsung Electronics and Taiwan Semiconductor Manufacturing Co. (TSMC) announced formal commitments to adopt ASML Holding NV’s High-Numerical-Aperture (High NA) extreme ultraviolet (EUV) lithography. Samsung will introduce the technology into high-volume DRAM manufacturing by 2028, while TSMC will begin using it for advanced-node logic production in 2030. Both companies also joined Intel in a consortium to develop 12-inch photomasks, with a pilot line slated for 2031 and production-ready systems targeted for 2033.
Background & Context
High NA EUV enables finer circuit patterns than earlier Low NA tools. ASML is the sole commercial supplier of EUV equipment, and its High NA scanners cost roughly $400 million each. Intel has already deployed High NA EUV in high-volume manufacturing, processing more than one million wafers on selected Core Ultra layers. Current 6-inch photomasks limit the exposure field of High NA tools, forcing “stitching” of multiple mask exposures—a source of complexity, yield loss, and higher cost. Transitioning to 12-inch masks is intended to eliminate stitching and boost fab productivity.
Data & Statistics
- Machine cost: ~$400 million per High NA scanner.
- ASML capacity plan: ~30 % increase in total EUV capacity for 2027.
- Productivity gain: Larger masks could raise scanner throughput by ? 40 %.
- Market position: Samsung is the world’s leading memory-chip maker; TSMC is the largest contract-foundry, together accounting for the majority of advanced-chip output.
Why It Matters / Impact
Adopting High NA EUV is expected to enable continued transistor scaling for AI accelerators, delivering smaller, faster, and more energy-efficient chips. If 12-inch masks deliver the projected 40 % productivity boost, fab output could rise while per-chip manufacturing costs fall, improving the economics of AI-focused semiconductor supply chains through 2033. The roadmap signals a coordinated industry response to the technical limits of current lithography, potentially shaping the cost structure of future data-center and high-performance-computing processors.
Official Statements & Responses
- Samsung said the partnership will “extend the DRAM scaling roadmap” and improve process efficiency, emphasizing its role in leading memory-chip innovation.
Verbatim Quotes
- “We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips,” — ASML CEO
- “That’s a huge opportunity, and of course that means a significant step in productivity,” — Marco Pieters, chief technology officer at ASML
Conflicting Reports & Gaps
All sources agree on Samsung’s 2028 DRAM target and TSMC’s 2030 advanced-node target. However, the timeline for the 12-inch mask rollout varies: some reports state a pilot line by 2031 with production readiness in 2033, while others describe “full-scale production” as occurring in 2033 without specifying the pilot date. No source provides detailed milestones for the first High NA layers that Samsung or TSMC will ship, leaving the near-term implementation schedule unclear.
