Advanced Packaging: The Next Bottleneck in AI Chip Production

The semiconductor industry is facing a critical bottleneck in the chipmaking process, specifically in advanced packaging, which is essential for integrating microchips into hardware that interacts with external systems. As artificial intelligence (AI) continues to drive demand for more complex chips, the need for advanced packaging solutions is becoming increasingly urgent. Currently, the majority of advanced packaging occurs in Asia, leading to concerns about capacity shortages as companies like Taiwan Semiconductor Manufacturing Co. (TSMC) and Intel ramp up their operations.

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TSMC is set to break ground on two new packaging plants in Arizona, while also expanding its facilities in Taiwan. The company's advanced packaging method, known as Chip on Wafer on Substrate (CoWoS), is experiencing an impressive 80% compound annual growth rate. Nvidia has secured a significant portion of TSMC's CoWoS capacity, highlighting the intense competition for advanced packaging resources. Meanwhile, Intel, which has struggled to attract external customers for its chip fabrication, has found a niche in packaging, serving clients like Amazon and Cisco.

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Advanced packaging has evolved from being an afterthought to a critical component of chip design. Analysts note that the integration of multiple dies, such as logic chips and high-bandwidth memory, into a single larger chip is essential for modern applications, particularly in AI. Patrick Moorhead, a chip analyst, emphasized that this shift has made packaging as vital as the chips themselves.

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Paul Rousseau, head of TSMC North America packaging solutions, stated that the demand for advanced packaging is "growing very substantially." He also noted that the complexity of chips has necessitated new packaging methods to extend the limits of Moore's Law. Mark Gardner, Intel's head of foundry services, expressed optimism about the company's packaging capabilities, indicating that there is "an inroad" to securing major chip manufacturing customers through advanced packaging.

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Despite the optimism surrounding advanced packaging, some experts warn that the current reliance on Asian facilities could pose risks to supply chains. John VerWey from Georgetown University's Center for Security and Emerging Technology cautioned that without proactive capital investments, the industry could quickly face bottlenecks as demand surges.

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As companies like Intel and TSMC expand their packaging capabilities, the landscape of semiconductor manufacturing is likely to shift. Intel's collaboration with Elon Musk for his Terafab project, which aims to produce 1 terrawatt of annual compute power for AI, could signal a new era in chip production. The completion of TSMC's U.S. packaging sites will also be closely watched, as it promises to reduce turnaround times and enhance operational efficiency.

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• “It can emerge as a bottleneck very quickly if people are not making the CapEx investments proactively to account for the surge in fab output that's going to be coming in the next couple of years,” — John VerWey, Georgetown University

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• “Now, obviously, we know it's as important as the die itself,” — Patrick Moorhead, Moor Insights & Strategy

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• “To have that capability right next to the fab in Arizona is going to make their customers very happy,” — Jan Vardaman, TechSearch International

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• “There's benefits of everything being in one place,” — Mark Gardner, Intel

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