Story perspectives

IBM Unveils 0.7nm Chip, 100 B Transistors, 50% Faster

6/26/2026

Summary

IBM Unveils Sub-nm

IBM announced its first sub-1 nm (0.7 nm) chip on June 25 2026 in Yorktown Heights, New York.
The fingernail-sized die holds about 100 billion transistors—nearly double the 2 nm density—and promises up to 50 percent higher performance or 70 percent better energy efficiency.
IBM’s three-dimensional nanostack architecture enabled functional CMOS inverters, ultra-thin dielectric bonding, a 40 percent SRAM density gain and a commercial rollout planned within five years with Rapidus, Lam Research and ASML’s High-NA EUV.

Summary

IBM Shares Surge

IBM’s shares rose over 6% in pre-market trading on June 25 2026 and later settled about 1.9% higher.
The stock has fallen roughly 11% so far this year, reflecting investor caution.
IBM’s licensing-only model, already used with Samsung and Japan’s Rapidus, may determine how the 0.7-nm design reaches fabs.
Professor Alan Woodward of Surrey University said IBM’s NanoStack resembles a 100-storey skyscraper, taller than 30-50-storey designs pursued by Samsung and Intel.

History

Historical Context

In 2010, Taiwan Semiconductor Manufacturing Company and GlobalFoundries began production of 28 nm chips with high-k metal gate technology, the node where cost per logic gate was lowest. Since 1997 the “nm” label has been a marketing term, and rising gate costs after 28 nm have pushed the industry toward sub-nanometer scaling efforts.

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IBM Unveils Sub-nm

IBM announced its first sub-1 nm (0.7 nm) chip on June 25 2026 in Yorktown Heights, New York.
The fingernail-sized die holds about 100 billion transistors—nearly double the 2 nm density—and promises up to 50 percent higher performance or 70 percent better energy efficiency.
IBM’s three-dimensional nanostack architecture enabled functional CMOS inverters, ultra-thin dielectric bonding, a 40 percent SRAM density gain and a commercial rollout planned within five years with Rapidus, Lam Research and ASML’s High-NA EUV.

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