Full Breakdown
IBM Unveils World's First Sub-1-Nanometer Chip Technology
6/26/2026, 11:38:19 AM
Breakthrough Overview
On June 25 2026, IBM announced a semiconductor prototype built on a 0.7-nanometer (7 angstrom) node, the first publicly disclosed sub-1 nm chip. The die, about the size of a fingernail, contains roughly 100 billion transistors—approximately twice the density of IBM’s 2 nm chip from 2021.
Technical Background
The chip uses IBM’s three-dimensional “nanostack” architecture, vertically stacking and staggering nanosheet transistors across two bonded wafers. Validation showed ultra-thin dielectric bonding, dual-channel engineering, functional CMOS inverters and a 40 % SRAM cell-area reduction.
Key Figures & Partnerships
Jay Gambetta, IBM Research Director and IBM Fellow, and Huiming Bu, IBM VP of silicon-technology research, led the work. Partners include Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions; IBM will soon use an ASML High-NA EUV tool at its Albany lab.
Data & Performance
- ~100 billion transistors on a fingernail-sized die (?2× density of 2 nm node).
- Projected up to 50 % higher performance and 70 % lower power versus the 2 nm node.
- SRAM cell area reduced by about 40 % for AI-focused memory.
Impact & Outlook
Nanostack targets AI accelerators, cloud services and high-performance computing, where higher transistor density without proportional power rise can extend Moore’s Law for at least a decade. IBM’s roadmap also envisions scaling below 1 nm to 0.1 nm nodes for future quantum wafers.
Official Statements
IBM’s press release says the 0.7 nm chip “demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions.” The company projects commercial adoption within five years and a roadmap to sub-0.1 nm scaling, positioning nanostack as a platform for CPUs, GPUs and memory.
Criticism & Opposition
Professor Alan Woodward of Surrey University described the nanostack as a “100-storey skyscraper” compared with rivals’ “30-50-storey” 3-D approaches, and warned that heat dissipation and thin inter-layer spacing could hinder reliable switching.
Conflicting Reports & Gaps
Sources differ on whether the “0.7 nm” label denotes a literal physical dimension or a generational node; IBM treats it as a sub-1 nm breakthrough. No foundry has been named for mass production, and the five-year timeline remains unverified by external partners.
Verbatim Quotes
- “With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency.” — Jay Gambetta, Director of IBM Research and IBM Fellow
- “Nanostack is more than simply making transistors smaller. It redefines how chips are built to significantly improve both performance and energy efficiency. This technology lays the foundation for the next era of computing.” — Jay Gambetta, IBM Research
- “We have entered a domain in semiconductor manufacturing [that] works between magic and physics,” — Huiming Bu, Vice President of IBM Semiconductors Global R&D
- “I think it's fair to say IBM's proposals are the most ambitious,” — Professor Alan Woodward, Surrey University
What’s Next
IBM will install a High-NA EUV lithography tool at its Albany site, continue work with Lam Research and Tokyo Electron, and later name a manufacturing partner for the sub-1 nm process. The Anderon quantum foundry and a roadmap to 0.1 nm nodes signal a longer-term strategy beyond the five-year horizon.
